Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device comprising a capacitor, a double-layer peripheral circuit wiring line and a double-layer metal contact, and to a fabrication method thereof.
Many efforts have been made to increase the height of a capacitor so as to maximize capacitance characteristics of the capacitor in a limited area of a substrate, thereby increasing a data storage capacity of the DRAM semiconductor device. As the design rule shrinks, the technology node of DRAM is decreasing. For this reason, it is particularly difficult not only to ensure the storage capacitance (Cs) to ensure a sensing margin when sensing data stored in a storage node, but also to reduce a parasitic bit-line capacitance (Cb).
In technology nodes of 32 nm or below, a dimension of patterns is rapidly becoming smaller, thus making it substantially more difficult to utilize cylindrical storage nodes which have conventionally been used. For this reason, efforts have been made to significantly increase the height of a capacitor to ensure its capacitance characteristics. However, as the capacitor height increases rapidly, a step height after etching of a plate node also increases rapidly so that the etch process margin becomes rapidly smaller. Also, in a peripheral region in which peripheral circuits such as a sense amplifier (SA) are formed, a pattern pitch of wiring lines interconnecting the peripheral circuits decreases rapidly, thus making it difficult to use single patterning to form a pattern of the peripheral circuit wiring lines. For this reason, efforts have been made to apply double patterning technology (DPT).
In addition, as the capacitor height increases, the height of a metal contact (M1C) connecting a peripheral circuit wiring line or a plate node to a metal line (M1) also increases. Also, metal contact holes for metal contacts become deeper, and thus an occurrence of bridges between the metal contact holes increases. As the metal contact holes get deeper, a size relative to a top of the metal contact holes increases, the interval margin between the metal contact holes gradually narrows, and the amount of oxides that are lost in a cleaning process after formation of the metal contact holes increases so that the size of the holes increases. As the size of the metal contact holes increases, bridges between the contact holes occur more frequently. If the interval between the metal contact holes is increased in order to overcome the above-described shortcomings, the area of the peripheral region will increase due to the increase in the interval together with the increase in the size of the metal contact holes. Therefore the size of the whole device chip will increase, thus causing undesired results.